1. Field of the Invention
The present invention is related to a latch circuit constituted by a signal detecting circuit, a circuit for firmly holding this signal detection state until a power supply is interrupted, and a circuit for firmly releasing the signal detection state when the power supply is again turned ON.
2. Description of the Related Art
Conventionally, a latch circuit capable of holding a signal detection state is typically arranged as shown in a circuit arrangement of FIG. 10 when an RS latch circuit is generally employed.
Referring now to the drawing, the conventional latch circuit will be explained.
First, a signal detecting circuit 2 detects an abnormal voltage of a specific terminal, an abnormal voltage of a power supply, and also an abnormal temperature. A detection output xe2x80x9cSSETXxe2x80x9d of this voltage detecting circuit 2 becomes an xe2x80x9cLxe2x80x9d level, namely active, and is connected to an SX terminal of an RS latch 1. The RS latch 1 is constituted by a 2-input NAND gate and a 3-input NAND gate. When the voltage detecting circuit 2 detects an abnormal voltage and an abnormal temperature, an output SCE of the 3-input NAND gate which constitutes the output of this RS latch 1 becomes an xe2x80x9cLxe2x80x9d level. At this time, both a signal xe2x80x9cSRSTX1xe2x80x9d and another signal xe2x80x9cSRSTX2xe2x80x9d are set to an xe2x80x9cHxe2x80x9d level, which are entered into the reset input of the RS latch 1. The output signal of the RS latch 1 constitutes an enable signal of another circuit, and also an enable signal of a system. For example, when the signal detecting circuit 2 detects that a short-circuit has occurred in a specific terminal, an abnormal heating phenomenon, or the like, the RS latch 1 causes operation of these failure circuits and systems to be stopped.
To again activate such a system which has stopped operating, the externally supplied reset signal SRSTX2 is input to the RS latch 1. Alternatively, since the power supply is again turned ON, the RS latch 1 is reset by receiving the signal SRSTX1 corresponding to the output signal of the power-ON reset circuit 3.
In general, there are some cases that a power-ON reset circuit may not firmly produce a reset signal, depending upon conditions occurring when a power supply is turned ON. As a result, even when such a power-ON reset circuit is not operable, a reset signal may be externally entered into a conventional latch circuit in order that an uncontrolled circuit may be reset.
For instance, in the case of a power-ON reset circuit shown in FIG. 11, when a power supply is turned ON, a potential of a node xe2x80x9cAxe2x80x9d is risen up to such a potential nearly equal to a power supply voltage because of a capacitive coupling phenomenon by a capacitor 5. Thereafter, electron charges stored in the capacitor 5 are extracted therefrom by resistor 6, so that the potential at the node A is decreased. Then, when this potential becomes lower than, or equal to an inverting voltage of an inverter 7 provided at a next stage, the output signal SRSTX of the power-ON reset circuit becomes an xe2x80x9cHxe2x80x9d level, and the reset signal is released.
In such a power-ON reset circuit, if the power supply voltage is risen at a slower speed than such a speed that the electron charges of the capacitor 5 are extracted by resistor 6, then this power-ON reset circuit cannot produce the reset signal.
However, when the power-ON reset circuit is arranged by having the externally entered reset input, the terminal for receiving such an externally-supplied reset signal is additionally required, or the circuit capable of recognizing the reset command must be employed. Furthermore, there are certain possibilities that releasing operation of the latching action happens to occur, which is not originally required, due to noise contained in the signal. As a result, this may deteriorate reliability of the system.
The present invention has been made to solve the above-described problem of the conventional reset circuit, and therefore, has an object to provide a reliable reset circuit.
To solve the problem as described above, according to a first aspect of the present invention, there is provided a latch circuit comprising means for detecting a signal, means for holding a signal detection condition and means for releasing the signal detection condition, characterized in that when a detection output produced from the detecting means is entered into the signal detection condition holding means, the signal detection condition holding means continuously holds the detection condition until a power supply is interrupted even when the detection output is not entered thereinto, the signal detection condition releasing means produces a release signal only when the power supply is turned ON, and once the signal detection condition holding means holds the signal detection condition, the signal detection condition holding means is reset to an undetection condition only when the power supply is interrupted and then is again turned ON.
According to the present invention as set forth in the first aspect thereof, since the signal and the command are not externally input so as to reset the latch circuit, this latch circuit may not be unnecessarily reset due to noise, etc.
Further, in a latch circuit according to a second aspect of the present invention, the latch circuit is characterized in that while the signal detection condition holding means holds the detection condition, the latch circuit stops operation of a circuit into which the output signal of the signal detection condition holding means is inputted.
According to the present invention as set forth in the second aspect thereof, once the signal condition detecting means detects the abnormal condition to latch the latch circuit, the system and the circuit are firmly stopped until the power supply is again turned ON. As a consequence, it is possible to avoid such an unstable condition where the latch circuit is unwantedly reset and both the activation and deactivation of the circuit and system are repeatedly carried out.
Further, in a latch circuit according to a third aspect of the present invention, the latch circuit is characterized in that the signal detection condition releasing means is comprised of means for detecting a power supply voltage, means for determining producing time of a release signal and means for shaping a waveform, whereby the signal detection condition releasing means is equal to a power-ON reset circuit operated in such a manner that the release signal is continuously output after the power supply is turned ON until a preselected time period has passed, or the power supply voltage has reached a constant power supply voltage.
According to the present invention as set forth in the third aspect thereof, any of the pulse width of the reset signal and of the power supply voltage can be optimized. This reset signal is used to reset the RS latch employed in the latch circuit. For instance, even when the power supply voltage is gradually raised, the power-ON reset circuit can continuously output the reset signal until the power supply voltage is increased up to such a voltage at which the circuit can be sufficiently operated. Even when the power supply voltage is rapidly raised, since the sufficiently wide pulse width of the signal capable of resetting the latch circuit can be secured, the RS latch can be firmly reset by merely turning ON the power supply again, without employing such a means for inputting the externally-supplied reset signal.
Further, in a latch circuit according to a fourth aspect of the present invention, the latch circuit is characterized in that the power supply voltage detecting means included in the power-ON reset circuit is constituted by a depletion-mode N-channel MIS transistor and an enhancement-mode P-channel MIS transistor, both a gate and a source of the depletion-mode N-channel MIS transistor are connected to the ground potential, a drain of the depletion-mode N-channel MIS transistor is commonly connected to a drain of the enhancement-mode P-channel MIS transistor, which constitutes an output terminal of the power supply voltage detecting means, and a source of the enhancement-mode P-type MIS transistor is connected to the power supply potential, a gate thereof is feedback-connected to the output of the power-ON reset circuit, and the latch circuit controls to turn ON the enhancement-mode P-channel MIS transistor only while the power-ON reset circuit produces a signal for releasing the detection condition.
According to the present invention as set forth in the fourth aspect thereof, in the power supply voltage detecting circuit, after the power supply voltage is increased higher than, or equal to the threshold voltage of the enhancement-mode P-channel MIS transistor, the output of the power supply voltage detecting circuit is increased from the ground potential. Furthermore, the power-ON reset circuit consumes the electric power only in the following case. That is, while this power-ON reset circuit produces the reset signal, only the penetration current flowing through both the enhancement-mode P-channel MIS transistor and the depletion-mode N-channel MIS transistor consumes the electric power. After the reset signal has been increased up to necessary time, or necessary power supply voltage, since the enhancement-mode P-channel MIS transistor is turned OFF, the circuit is brought into a static condition, so that the latch circuit may consume only very low electric power except when the power supply is turned ON.
Further, in a latch circuit according to a fifth aspect of the present invention, the latch circuit is characterized in that an absolute value of a threshold voltage of the P-channel MIS transistor which constitutes the power supply voltage detecting means included in the power-ON reset circuit is made higher than an absolute value of a threshold voltage of the P-channel MIS transistor and also an absolute value of a threshold voltage of the N-channel MIS transistor, which constitute the signal detection condition holding means.
According to the present invention as set forth in the fifth aspect thereof, since the power supply voltage detecting circuit continuously outputs the ground potential until such a power supply voltage under which the Rs latch circuit holding the detection condition is operated under stable condition, the latch circuit can be firmly reset by the produced reset signal.
Further, in a latch circuit according to a sixth aspect of the present invention, the latch circuit is characterized in that the release signal producing time determining means included in the power-ON reset circuit is constituted by a first capacitor, one terminal of which is connected to a power supply potential, a depletion-mode N-channel MIS transistor having a drain connected to another terminal of the first capacitor, a first enhancement-mode N-channel MIS transistor having a drain commonly connected to both a gate and a source of the depletion-mode N-channel MIS transistor, an inverter circuit having an input which corresponds to a junction point between the first capacitor and the drain of the depletion-mode N-channel MIS transistor, a second capacitor connected between an output terminal of the inverter circuit and the ground potential and a second enhancement-mode N-channel MIS transistor in which the output terminal of the inverter circuit is connected to a gate thereof, a drain thereof is connected to the input of the inverter circuit, and a source thereof is connected to the ground potential; wherein the gate of the first enhancement-mode N-channel MIS transistor is connected to the output terminal of the voltage detecting means and an output of the inverter circuit constitutes the output of the release signal producing time determining means.
According to the present invention as set forth in the sixth aspect thereof, the output of the power supply voltage detecting means as set forth in the third and fourth aspect thereof is connected to the gate of the first enhancement-mode N-channel MIS transistor so as to control the ON/OFF state of this MIS transistor. AS a result, until the output voltage of the power supply voltage detecting means becomes higher than the threshold voltage of the first enhancement-mode N-channel MIS transistor, the potential at the junction point between the first capacitor and the depletion-mode N-channel MIS transistor is maintained at a potential nearly equal to the power supply potential, and the power-ON reset circuit continuously outputs the reset signal. Furthermore, after the first enhancement-mode N-channel MIS transistor has been turned ON, since the electron charges stored in the first capacitor are extracted by way of the depletion-mode N-channel IS transistor functioning as the constant current element, the potential at another terminal of the first capacitor is gradually decreased. Then, the reset signal is output until this potential is decreased lower than, or equal to, the inverting voltage of the inverter connected at the next stage.
Further, in a latch circuit according to a seventh aspect of the present invention, the latch circuit is characterized in that the inverter circuit included in the release signal producing time determining means is constituted by an enhancement-mode P-channel MIS transistor and an enhancement-mode N-channel MIS transistor; and an absolute value of a threshold voltage of the enhancement-mode P-channel MIS transistor is made higher than an absolute value of a threshold voltage of the P-channel MIS transistor and also higher than an absolute value of a threshold voltage of the N-channel MIS transistor, which constitute the signal detection condition holding means.
According to the present invention as set forth in the seventh aspect thereof, under such a very low voltage condition that the circuit operation becomes unstable, as to the P-channel MIS transistor and the N-channel MIS transistor, which constitute the inverter, the N-channel MIS transistor is always and easily turned ON in advance. The inverter readily outputs the xe2x80x9cLxe2x80x9d level signal. As a consequence, the power-ON reset circuit can more firmly output the reset signal when the power supply is turned ON.
Further, in a latch circuit according to an eighth aspect of the present invention, the latch circuit is characterized in that the inverter circuit included in the release signal producing time determining means is constituted by an enhancement-mode P-channel MIS transistor and an enhancement-mode N-channel MIS transistor; and an absolute value of a threshold voltage of the enhancement-mode N-channel MIS transistor is made lower than an absolute value of a threshold voltage of the P-channel MIS transistor and also lower than an absolute value of a threshold voltage of the N-channel MIS transistor, which constitute the signal detection condition holding means.
According to the present invention as set forth in the eighth aspect thereof, under such a very low voltage condition that the circuit operation becomes unstable, as to the P-channel MIS transistor and the N-channel MIS transistor, which constitute the inverter, the N-channel MIS transistor is always and easily turned ON in advance. The inverter readily outputs the xe2x80x9cLxe2x80x9d level signal. As a consequence, the power-ON reset circuit can more firmly output the reset signal when the power supply is turned ON.
Further, in a latch circuit according to a ninth aspect of the present invention, the latch circuit is characterized in that the signal detected by the signal detecting means is used to detect that the power supply voltage is lower than, or equal to a specific voltage.
According to the present invention as set forth in the ninth aspect thereof, the operation of the system can be firmly stopped in the case that the operation voltage is out of the power supply voltage range where the circuit can be operated under stable condition. Thus, operational runaway of the system can be avoided.
Further, in a latch circuit according to a tenth aspect of the present invention, the latch circuit is characterized in that the signal detected by the signal detecting means is used to detect that the power supply voltage is higher than, or equal to a specific voltage.
According to the present invention as set forth in the tenth aspect thereof, the operation of the system can be firmly stopped in the case that the operation voltage is out of the power supply voltage range where the circuit can be operated under stable condition. Thus, operational runaway of the system can be avoided.
Further, in a latch circuit according to an eleventh aspect of the present invention, the latch circuit is characterized in that the signal detected by the signal detecting means is used to detect that a voltage of a specific terminal is lower than, or equal to a specific voltage.
According to the present invention as set forth in the eleventh aspect thereof, for example, even when an output of a regulator circuit is short-circuited, the latch circuit can firmly stop operation of the system, and also can surely avoid break-down and operational runaway of the circuit.
Further, in a latch circuit according to a twelfth aspect of the present invention, the latch circuit is characterized in that the signal detected by the signal detecting means is used to detect that a voltage of a specific terminal is higher than, or equal to a specific voltage.
According to the present invention as set forth in the twelfth aspect thereof, for example, even when an excessively high voltage is applied to a specific input terminal, the latch circuit can firmly stop operation of the system, and also can surely avoid break-down and operational runaway of the circuit.
Further, in a latch circuit according to a thirteenth aspect of the present invention, the latch circuit is characterized in that the signal detected by the signal detecting means is used to detect that an ambient temperature, or a temperature of a semiconductor substrate where the latch circuit is constituted is higher than a specific temperature.
According to the present invention as set forth in the thirteenth aspect thereof, even when the ambient temperature, or the temperature of the semiconductor substrate is increased higher than the necessary temperature, the latch circuit can firmly stop operation of the system, and also can surely avoid break-down and operational runaway of the circuit.
Further, in a latch circuit according to a fourteenth aspect of the present invention, the latch circuit is characterized in that the signal detected by the signal detecting means is used to detect that an ambient temperature, or a temperature of a semiconductor substrate where the latch circuit is constituted is lower than a specific temperature.
According to the present invention as set forth in the fourteenth aspect thereof, even when the ambient temperature, or the temperature of the semiconductor substrate is increased lower than the necessary temperature, the latch circuit can firmly stop operation of the system. In general, when the temperature is low in an MIS type integrated circuit, this MIS type integrated circuit easily produce noise, and/or may readily become sensitive with respect to this noise. As a result, this latch circuit can avoid erroneous operation.
Further, in a latch circuit according to a fifteenth aspect of the present invention, the latch circuit is characterized in that a circuit which is stopped while the signal detection condition holding means holds the detection condition corresponds to a voltage detecting circuit.
According to the present invention as set forth in the fifteenth aspect thereof, even when the voltage of the detected signal is oscillated at the voltage nearly equal to the detection voltage of the voltage detecting circuit, the latch circuit can surely stop operation of the system.
Further, in a latch circuit according to a sixteenth aspect of the present invention, the latch circuit is characterized in that a circuit which is stopped while the signal detection condition holding means holds the detection condition, corresponds to a temperature detecting circuit.
According to the present invention as set forth in the sixteenth aspect thereof, even when the ambient temperature, or the temperature of the semiconductor substrate is vibrated near the detection temperature, the latch circuit can firmly stop operation of the system.
Further, in a latch circuit according to a seventeenth aspect of the present invention, the latch circuit is characterized in that a circuit which is stopped while the signal detection condition holding means holds the detection condition corresponds to a series-type voltage regulating circuit.
According to the present invention as set forth in the seventeenth aspect thereof, for instance, when the output of the series-type regulating circuit is short-circuited, since the latch circuit can stop operation of the system by detecting such a short-circuit condition, both break-down and operational runaway can be avoided.
Further, in a latch circuit according to an eighteenth aspect of the present invention, the latch circuit is characterized in that a circuit which is stopped while the signal detection condition holding means holds the detection condition corresponds to a switching type voltage regulating circuit.
According to the present invention as set forth in the eighteenth aspect thereof, for instance, when the output of the switching-type regulating circuit is short-circuited, since the latch circuit can stop operation of the system by detecting such a short-circuit condition, both break-down and operational runaway can be avoided.